Evaluation of monolithic 3-D logic circuits and 6T SRAMs with InGaAs-n/Ge-p ultra-thin-body MOSFETs

This paper evaluates monolithic 3-D logic circuits and 6T SRAMs composed of InGaAs-n/Ge-p ultra-thin-body MOSFETs while considering interlayer coupling through TCAD mixedmode model. This paper indicates that monolithic 3-D InGaAs/Ge logic circuits provide equal leakage and better delay performance compared with planar 2-D structure through optimized 3-D layout. The monolithic 3-D InGaAs/Ge 6T SRAMs can simultaneously improve the cell stability and performance through optimized 3-D layout. We suggest two 3-D SRAM layout designs for high performance and low power applications, respectively. Moreover, with optimized 3-D layout designs, InGaAs/Ge logic circuits exhibit larger delay improvement, and the 6T SRAMs exhibit larger read access time and time-to-write improvement compared with Si counterparts.