Evaluation of InAs QWFET for low power logic applications

Edward Yi Chang, Chien I. Kuo, Heng-Tung Hsu, Yasuyuki Miyamoto, Chia Ta Chang, Chien Ying Wu

研究成果: Conference contribution同行評審

1 引文 斯高帕斯(Scopus)

摘要

An eighty nanometer gate length InAs quantum well field effect transistors has been fabricated and the digital characteristics were evaluated. The devices show a drain-source current of 1015 mA/mm and a peak gm of 1920 mS/mm at VDS = 0.5 V. The fT and fmax are 340 GHz and 220 GHz at VDS = 0.4 V, respectively. A low delay time (C totalV/ION) of 0.54 ps was also achieved. These excellent results indicate the InAs devices are the great potential option for the future low-power logic applications at post-Si CMOS technology.

原文English
主出版物標題ECS Transactions - ISTC/CSTIC 2009 (CISTC)
頁面863-868
頁數6
版本1 PART 2
DOIs
出版狀態Published - 2009
事件ISTC/CSTIC 2009 (CISTC) - Shanghai, 中國
持續時間: 19 3月 200920 3月 2009

出版系列

名字ECS Transactions
號碼1 PART 2
18
ISSN(列印)1938-5862
ISSN(電子)1938-6737

Conference

ConferenceISTC/CSTIC 2009 (CISTC)
國家/地區中國
城市Shanghai
期間19/03/0920/03/09

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