Evaluation of a 100-nm Gate Length E-Mode InAs High Electron Mobility Transistor with Ti/Pt/Au Ohmic Contacts and Mesa Sidewall Channel Etch for High-Speed and Low-Power Logic Applications
- Jing Neng Yao
- , Yueh Chin Lin
- , Heng-Tung Hsu
- , Kai Chun Yang
- , Hisang Hua Hsu
- , Simon M. Sze
- , Edward Yi Chang*
*此作品的通信作者
研究成果: Article › 同行評審
5
引文
斯高帕斯（Scopus）