Estimating likelihood of correctness for error candidates to assist debugging faulty hdl designs

Tai Ying Jiang; Jing Yang Jou; Chien-Nan Liu

doi:10.1109/ISCAS.2005.1465927

Estimating likelihood of correctness for error candidates to assist debugging faulty hdl designs

Tai Ying Jiang, Jing Yang Jou, Chien-Nan Liu

電子研究所

研究成果: Conference article › 同行評審

14 引文斯高帕斯（Scopus）

摘要

Debugging priority is a helpful technique to assist debugging faulty HDL designs [9]. However, debugging priority obtained by sorting confidence score is not good enough due to the inaccuracy in estimating likelihood of correctness for error candidates. Therefore, we developed Refined Confidence Score for deriving better debugging priority.

原文	English
文章編號	1465927
頁（從 - 到）	5682-5685
頁數	4
期刊	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1465927
出版狀態	Published - 2005
事件	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, 日本持續時間: 23 5月 2005 → 26 5月 2005

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10.1109/ISCAS.2005.1465927

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title = "Estimating likelihood of correctness for error candidates to assist debugging faulty hdl designs",

abstract = "Debugging priority is a helpful technique to assist debugging faulty HDL designs [9]. However, debugging priority obtained by sorting confidence score is not good enough due to the inaccuracy in estimating likelihood of correctness for error candidates. Therefore, we developed Refined Confidence Score for deriving better debugging priority.",

author = "Jiang, {Tai Ying} and Jou, {Jing Yang} and Chien-Nan Liu",

year = "2005",

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language = "English",

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journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

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AU - Jiang, Tai Ying

AU - Jou, Jing Yang

AU - Liu, Chien-Nan

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N2 - Debugging priority is a helpful technique to assist debugging faulty HDL designs [9]. However, debugging priority obtained by sorting confidence score is not good enough due to the inaccuracy in estimating likelihood of correctness for error candidates. Therefore, we developed Refined Confidence Score for deriving better debugging priority.

AB - Debugging priority is a helpful technique to assist debugging faulty HDL designs [9]. However, debugging priority obtained by sorting confidence score is not good enough due to the inaccuracy in estimating likelihood of correctness for error candidates. Therefore, we developed Refined Confidence Score for deriving better debugging priority.

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U2 - 10.1109/ISCAS.2005.1465927

DO - 10.1109/ISCAS.2005.1465927

M3 - Conference article

AN - SCOPUS:47949102761

SN - 0271-4310

SP - 5682

EP - 5685

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 1465927

T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

Estimating likelihood of correctness for error candidates to assist debugging faulty hdl designs

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