TY - GEN
T1 - ESD test methods on integrated circuits
T2 - 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001
AU - Ker, Ming-Dou
AU - Peng, Jeng Jie
AU - Jiang, Hsin Chin
PY - 2001/12/1
Y1 - 2001/12/1
N2 - ESD phenomenon has become a serious problem for IC products fabricated by deep-submicron CMOS technologies. To qualify the ESD immunity of IC products, there are some test methods and standards developed by some organizations, which are ESDA, AEC, EINJEDEC, and MIL-STD organizations. ESD events have been classified into 4 models, which are HBM, MM, CDM, and SDM. Besides, there are 4 modes of pin combinations for ESD zapping on the IC pins, which are specified as (1) Pin-to-VSS, (2) Pin-to-VDD, (3) Pin-to-Pin, and (4) VDD-to-VSS. All the test methods are designed to evaluate the ESD immunity of IC products. The zap number, zap interval, and sample size are all well defined in the related industrial standards. This paper provides an overview among ESD test methods on IC products. In general, the commercial IC products are requested to sustain at least 2-kV HBM, 200-V MM, and 1-kV CDM ESD stresses.
AB - ESD phenomenon has become a serious problem for IC products fabricated by deep-submicron CMOS technologies. To qualify the ESD immunity of IC products, there are some test methods and standards developed by some organizations, which are ESDA, AEC, EINJEDEC, and MIL-STD organizations. ESD events have been classified into 4 models, which are HBM, MM, CDM, and SDM. Besides, there are 4 modes of pin combinations for ESD zapping on the IC pins, which are specified as (1) Pin-to-VSS, (2) Pin-to-VDD, (3) Pin-to-Pin, and (4) VDD-to-VSS. All the test methods are designed to evaluate the ESD immunity of IC products. The zap number, zap interval, and sample size are all well defined in the related industrial standards. This paper provides an overview among ESD test methods on IC products. In general, the commercial IC products are requested to sustain at least 2-kV HBM, 200-V MM, and 1-kV CDM ESD stresses.
UR - http://www.scopus.com/inward/record.url?scp=71049180243&partnerID=8YFLogxK
U2 - 10.1109/ICECS.2001.957647
DO - 10.1109/ICECS.2001.957647
M3 - Conference contribution
AN - SCOPUS:71049180243
SN - 0780370570
SN - 9780780370579
T3 - Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems
SP - 1011
EP - 1014
BT - ICECS 2001 - 8th IEEE International Conference on Electronics, Circuits and Systems
Y2 - 2 September 2001 through 5 September 2001
ER -