ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

Ming-Dou Ker; Chung-Yu Wu; Hun Hsien Chang; Chien Chang Huang; Chau Neng Wu; Ta Lee Yu

doi:10.1109/HKEDM.1996.566328

ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

Ming-Dou Ker^*, Chung-Yu Wu, Hun Hsien Chang, Chien Chang Huang, Chau Neng Wu, Ta Lee Yu

^*此作品的通信作者

電子研究所

研究成果: Paper › 同行評審

摘要

Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique. ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS IC's can be effectively improved.

原文	English
頁面	98-101
頁數	4
DOIs	https://doi.org/10.1109/HKEDM.1996.566328
出版狀態	Published - 1996
事件	Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting - Hong Kong, Hong Kong 持續時間: 29 6月 1996 → 29 6月 1996

Conference

Conference	Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting
城市	Hong Kong, Hong Kong
期間	29/06/96 → 29/06/96

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10.1109/HKEDM.1996.566328

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引用此

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title = "ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology",

abstract = "Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique. ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS IC's can be effectively improved.",

author = "Ming-Dou Ker and Chung-Yu Wu and Chang, {Hun Hsien} and Huang, {Chien Chang} and Wu, {Chau Neng} and Yu, {Ta Lee}",

year = "1996",

doi = "10.1109/HKEDM.1996.566328",

language = "English",

pages = "98--101",

note = "Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting ; Conference date: 29-06-1996 Through 29-06-1996",

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T1 - ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

AU - Ker, Ming-Dou

AU - Wu, Chung-Yu

AU - Chang, Hun Hsien

AU - Huang, Chien Chang

AU - Wu, Chau Neng

AU - Yu, Ta Lee

PY - 1996

Y1 - 1996

N2 - Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique. ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS IC's can be effectively improved.

AB - Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique. ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS IC's can be effectively improved.

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U2 - 10.1109/HKEDM.1996.566328

DO - 10.1109/HKEDM.1996.566328

M3 - Paper

AN - SCOPUS:0030409171

SP - 98

EP - 101

T2 - Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting

Y2 - 29 June 1996 through 29 June 1996

ER -

ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

摘要

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