Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique. ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS IC's can be effectively improved.
|出版狀態||Published - 1 12月 1996|
|事件||Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting - Hong Kong, Hong Kong|
持續時間: 29 6月 1996 → 29 6月 1996
|Conference||Proceedings of the 1996 3rd IEEE Hong Kong Electron Devices Meeting|
|城市||Hong Kong, Hong Kong|
|期間||29/06/96 → 29/06/96|