ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design

T. Y. Chen*, Ming-Dou Ker

*此作品的通信作者

    研究成果: Paper同行評審

    7 引文 斯高帕斯(Scopus)

    摘要

    The operation principles of gate-driven design and substrate-triggered design for ESD (ElectroStatic Discharge) protection are first explained by energy-band diagrams in this paper. The on-chip ESD protection devices realized in 0.18-μm and 0.35-μm CMOS processes are used to verify the efficiency of gate-driven or substrate-triggered designs. The substrate-triggered design can effectively and continually improve ESD robustness of protection devices than the gate-driven design. The HBM (Human-Body-Model) ESD level of NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by the substrate-triggered design. But, the gate-driven design cannot continually improve the ESD level of the same device in the sub-quarter-micron CMOS process.

    原文English
    頁面232-235
    頁數4
    DOIs
    出版狀態Published - 18 4月 2001
    事件2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings - Hsinchu, Taiwan
    持續時間: 18 4月 200120 4月 2001

    Conference

    Conference2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings
    國家/地區Taiwan
    城市Hsinchu
    期間18/04/0120/04/01

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