ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design

The operation principles of gate-driven design and substrate-triggered design for ESD (ElectroStatic Discharge) protection are first explained by energy-band diagrams in this paper. The on-chip ESD protection devices realized in 0.18-μm and 0.35-μm CMOS processes are used to verify the efficiency of gate-driven or substrate-triggered designs. The substrate-triggered design can effectively and continually improve ESD robustness of protection devices than the gate-driven design. The HBM (Human-Body-Model) ESD level of NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by the substrate-triggered design. But, the gate-driven design cannot continually improve the ESD level of the same device in the sub-quarter-micron CMOS process.