ESD protection for mixed-voltage I/O in low- voltage thin-oxide CMOS

Ming-Dou Ker*, Wei Jen Chang, Chang Tzu Wang, Wen Yi Chen

*此作品的通信作者

    研究成果: Conference contribution同行評審

    12 引文 斯高帕斯(Scopus)

    摘要

    An ESD protection design for 1.2V/2.5V mixed-voltage I/O interfaces is discussed. A high-voltage-tolerant power-rail ESD clamp circuit is used; it is realized with low-voltage devices in a 0.13μm CMOS process. The four-mode ESD stresses on the mixed-voltage I/O pad and the whole-chip pin-to-pin ESD protection can be discharged by the proposed ESD protection scheme.

    原文English
    主出版物標題2006 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
    DOIs
    出版狀態Published - 1 12月 2006
    事件2006 IEEE International Solid-State Circuits Conference, ISSCC - San Francisco, CA, United States
    持續時間: 6 2月 20069 2月 2006

    出版系列

    名字Digest of Technical Papers - IEEE International Solid-State Circuits Conference
    ISSN(列印)0193-6530

    Conference

    Conference2006 IEEE International Solid-State Circuits Conference, ISSCC
    國家/地區United States
    城市San Francisco, CA
    期間6/02/069/02/06

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