A novel ESD protection circuit, which first combines the advantages of complementary low-voltage-trigger SCR devices and the gate-couple technique, is proposed to more effectively protect the thinner gate oxide of deep submicron CMOS IC's without adding extra ESD-implant mask. Experimental results have verified its excellent ESD-protection capability.
|頁（從 - 到）||543-546|
|期刊||Technical Digest - International Electron Devices Meeting|
|出版狀態||Published - 1 12月 1995|
|事件||Proceedings of the 1995 International Electron Devices Meeting, IEDM'95 - Washington, DC, USA|
持續時間: 10 12月 1995 → 13 12月 1995