ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure

Ming-Dou Ker; Hun Hsien Chang; Chung-Yu Wu

doi:10.1109/IEDM.1995.499279

ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure

Ming-Dou Ker^*, Hun Hsien Chang, Chung-Yu Wu

^*此作品的通信作者

電子研究所

研究成果: Conference article › 同行評審

7 引文斯高帕斯（Scopus）

摘要

A novel ESD protection circuit, which first combines the advantages of complementary low-voltage-trigger SCR devices and the gate-couple technique, is proposed to more effectively protect the thinner gate oxide of deep submicron CMOS IC's without adding extra ESD-implant mask. Experimental results have verified its excellent ESD-protection capability.

原文	English
頁（從 - 到）	543-546
頁數	4
期刊	Technical Digest - International Electron Devices Meeting
DOIs	https://doi.org/10.1109/IEDM.1995.499279
出版狀態	Published - 1995
事件	Proceedings of the 1995 International Electron Devices Meeting, IEDM'95 - Washington, DC, USA 持續時間: 10 12月 1995 → 13 12月 1995

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10.1109/IEDM.1995.499279

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title = "ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure",

abstract = "A novel ESD protection circuit, which first combines the advantages of complementary low-voltage-trigger SCR devices and the gate-couple technique, is proposed to more effectively protect the thinner gate oxide of deep submicron CMOS IC's without adding extra ESD-implant mask. Experimental results have verified its excellent ESD-protection capability.",

author = "Ming-Dou Ker and Chang, {Hun Hsien} and Chung-Yu Wu",

year = "1995",

doi = "10.1109/IEDM.1995.499279",

language = "English",

pages = "543--546",

journal = "Technical Digest - International Electron Devices Meeting",

issn = "0163-1918",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "Proceedings of the 1995 International Electron Devices Meeting, IEDM'95 ; Conference date: 10-12-1995 Through 13-12-1995",

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TY - JOUR

T1 - ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure

AU - Ker, Ming-Dou

AU - Chang, Hun Hsien

AU - Wu, Chung-Yu

PY - 1995

Y1 - 1995

N2 - A novel ESD protection circuit, which first combines the advantages of complementary low-voltage-trigger SCR devices and the gate-couple technique, is proposed to more effectively protect the thinner gate oxide of deep submicron CMOS IC's without adding extra ESD-implant mask. Experimental results have verified its excellent ESD-protection capability.

AB - A novel ESD protection circuit, which first combines the advantages of complementary low-voltage-trigger SCR devices and the gate-couple technique, is proposed to more effectively protect the thinner gate oxide of deep submicron CMOS IC's without adding extra ESD-implant mask. Experimental results have verified its excellent ESD-protection capability.

UR - http://www.scopus.com/inward/record.url?scp=0029547091&partnerID=8YFLogxK

U2 - 10.1109/IEDM.1995.499279

DO - 10.1109/IEDM.1995.499279

M3 - Conference article

AN - SCOPUS:0029547091

SN - 0163-1918

SP - 543

EP - 546

JO - Technical Digest - International Electron Devices Meeting

JF - Technical Digest - International Electron Devices Meeting

T2 - Proceedings of the 1995 International Electron Devices Meeting, IEDM'95

Y2 - 10 December 1995 through 13 December 1995

ER -

ESD protection for deep-submicron CMOS technology using gate-couple CMOS-trigger lateral SCR structure

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