ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices

Ming-Dou Ker

doi:10.1109/ASIC.1997.617022

ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices

Ming-Dou Ker^*

^*此作品的通信作者

電子研究所

研究成果: Conference article › 同行評審

9 引文斯高帕斯（Scopus）

摘要

A practical solution has been proposed to safely apply the LVTSCR (low-voltage-trigger SCR) device for output ESD (electrostatic discharge) protection in the advanced submicron CMOS ASIC's without being accidentally triggered on in the noisy operating environments. By increasing the trigger current of the LVTSCR device up to 200 mA, a noise margin greater than VDD+12 V (VSS-12 V) against the accidental triggering due to the overshooting (undershooting) noise pulses has been practically confirmed by the experimental results. Due to remaining a lower trigger voltage, this solution can still provide effective ESD protection for output transistors but only occupies a small layout area.

原文	English
頁（從 - 到）	283-286
頁數	4
期刊	Proceedings of the Annual IEEE International ASIC Conference and Exhibit
DOIs	https://doi.org/10.1109/ASIC.1997.617022
出版狀態	Published - 1997
事件	Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA 持續時間: 7 9月 1997 → 10 9月 1997

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10.1109/ASIC.1997.617022

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title = "ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices",

abstract = "A practical solution has been proposed to safely apply the LVTSCR (low-voltage-trigger SCR) device for output ESD (electrostatic discharge) protection in the advanced submicron CMOS ASIC's without being accidentally triggered on in the noisy operating environments. By increasing the trigger current of the LVTSCR device up to 200 mA, a noise margin greater than VDD+12 V (VSS-12 V) against the accidental triggering due to the overshooting (undershooting) noise pulses has been practically confirmed by the experimental results. Due to remaining a lower trigger voltage, this solution can still provide effective ESD protection for output transistors but only occupies a small layout area.",

author = "Ming-Dou Ker",

year = "1997",

doi = "10.1109/ASIC.1997.617022",

language = "English",

pages = "283--286",

journal = "Proceedings of the Annual IEEE International ASIC Conference and Exhibit",

issn = "1063-0988",

note = "Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit ; Conference date: 07-09-1997 Through 10-09-1997",

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T1 - ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices

AU - Ker, Ming-Dou

PY - 1997

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N2 - A practical solution has been proposed to safely apply the LVTSCR (low-voltage-trigger SCR) device for output ESD (electrostatic discharge) protection in the advanced submicron CMOS ASIC's without being accidentally triggered on in the noisy operating environments. By increasing the trigger current of the LVTSCR device up to 200 mA, a noise margin greater than VDD+12 V (VSS-12 V) against the accidental triggering due to the overshooting (undershooting) noise pulses has been practically confirmed by the experimental results. Due to remaining a lower trigger voltage, this solution can still provide effective ESD protection for output transistors but only occupies a small layout area.

AB - A practical solution has been proposed to safely apply the LVTSCR (low-voltage-trigger SCR) device for output ESD (electrostatic discharge) protection in the advanced submicron CMOS ASIC's without being accidentally triggered on in the noisy operating environments. By increasing the trigger current of the LVTSCR device up to 200 mA, a noise margin greater than VDD+12 V (VSS-12 V) against the accidental triggering due to the overshooting (undershooting) noise pulses has been practically confirmed by the experimental results. Due to remaining a lower trigger voltage, this solution can still provide effective ESD protection for output transistors but only occupies a small layout area.

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U2 - 10.1109/ASIC.1997.617022

DO - 10.1109/ASIC.1997.617022

M3 - Conference article

AN - SCOPUS:0030689966

SN - 1063-0988

SP - 283

EP - 286

JO - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

JF - Proceedings of the Annual IEEE International ASIC Conference and Exhibit

T2 - Proceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit

Y2 - 7 September 1997 through 10 September 1997

ER -

ESD protection for CMOS ASIC in noisy environments with high-current low-voltage triggering SCR devices

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