ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC

Chia Tsen Dai, Ming Dou Ker

研究成果: Conference contribution同行評審

5 引文 斯高帕斯(Scopus)

摘要

For high-voltage (HV) application, an on-chip ESD protection solution has been proposed in a 0.25-μm HV BCD process by using low-voltage (LV) p-type devices with the stacked configuration. Experimental results in silicon chip have verified that the proposed design can successfully protect the 60-V pins of a battery-monitoring IC against over 8-kV human-body-mode (HBM) ESD stress.

原文English
主出版物標題Proceedings - 28th IEEE International System on Chip Conference, SOCC 2015
編輯Thomas Buchner, Danella Zhao, Karan Bhatia, Ramalingam Sridhar
發行者IEEE Computer Society
頁面380-383
頁數4
ISBN(電子)9781467390934
DOIs
出版狀態Published - 12 2月 2016
事件28th IEEE International System on Chip Conference, SOCC 2015 - Beijing, China
持續時間: 8 9月 201511 9月 2015

出版系列

名字International System on Chip Conference
2016-February
ISSN(列印)2164-1676
ISSN(電子)2164-1706

Conference

Conference28th IEEE International System on Chip Conference, SOCC 2015
國家/地區China
城市Beijing
期間8/09/1511/09/15

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