ESD protection design with latchup-free immunity in 120V SOI process

Yi Jie Huang, Ming-Dou Ker, Yeh Jen Huang, Chun Chien Tsai, Yeh Ning Jou, Geeng Lih Lin

    研究成果: Conference contribution同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    Electrostatic discharge (ESD) protection with low-voltage (LV) field-oxide devices in stacked configuration are proposed for high-voltage (HV) applications in a 0.5-μm 120V SOI process. Stacked LV field-oxide devices with different stacking numbers have been verified in silicon chip to exhibit both of high ESD robustness and latchup-free immunity for HV applications.

    原文English
    主出版物標題2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
    發行者Institute of Electrical and Electronics Engineers Inc.
    ISBN(電子)9781509002597
    DOIs
    出版狀態Published - 20 11月 2015
    事件IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015 - Rohnert Park, United States
    持續時間: 5 10月 20158 10月 2015

    出版系列

    名字2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015

    Conference

    ConferenceIEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2015
    國家/地區United States
    城市Rohnert Park
    期間5/10/158/10/15

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