@inproceedings{aa641f465fcd4ebbb49268310c19eeb8,
title = "ESD protection design on analog pin with very low input capacitance for RF or current-mode applications",
abstract = "An ESD design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp devices in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such smaller device dimensions, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ∼1.0 pF (including the bond pad capacitance) for high-frequency applications.",
author = "Ming-Dou Ker and Chen, {Tung Yang} and Chung-Yu Wu and Chang, {Hun Hsien}",
year = "1999",
month = jan,
day = "1",
doi = "10.1109/ASIC.1999.806533",
language = "English",
series = "Proceedings - 12th Annual IEEE International ASIC/SOC Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "352--356",
booktitle = "Proceedings - 12th Annual IEEE International ASIC/SOC Conference",
address = "United States",
note = "12th Annual IEEE International ASIC/SOC Conference ; Conference date: 15-09-1999 Through 18-09-1999",
}