TY - GEN
T1 - ESD protection design in a 0.18-/spl mu/m salicide CMOS technology by using substrate-triggered technique
AU - Ker, Ming-Dou
AU - Chen, Tung Yang
AU - Win, Chung-Yu
PY - 2001/12/1
Y1 - 2001/12/1
N2 - A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output and power pads have been fabricated and verified in a 0.18-/spl mu/m salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300 /spl mu/m/0.3 /spl mu/m can be improved from the original 0.8 kV to become 3.3 kV by this substrate-triggered technique.
AB - A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output and power pads have been fabricated and verified in a 0.18-/spl mu/m salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300 /spl mu/m/0.3 /spl mu/m can be improved from the original 0.8 kV to become 3.3 kV by this substrate-triggered technique.
UR - http://www.scopus.com/inward/record.url?scp=84888038303&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2001.922347
DO - 10.1109/ISCAS.2001.922347
M3 - Conference contribution
AN - SCOPUS:84888038303
SN - 0780366859
SN - 9780780366855
T3 - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
SP - 754
EP - 757
BT - ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
T2 - 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
Y2 - 6 May 2001 through 9 May 2001
ER -