ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique

Ming-Dou Ker; T. Y. Chen; Chung-Yu Wu

ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique

Ming-Dou Ker^*, T. Y. Chen, Chung-Yu Wu

^*此作品的通信作者

研究成果: Conference article › 同行評審

2 引文斯高帕斯（Scopus）

摘要

A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output, and power pads have been fabricated and verified in a 0.18-μm salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by this substrate-triggered technique.

原文	English
文章編號	922347
頁（從 - 到）	IV754-IV757
頁數	4
期刊	Materials Research Society Symposium - Proceedings
卷	626
出版狀態	Published - 4月 2000
事件	Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications - San Francisco, CA, United States 持續時間: 24 4月 2000 → 27 4月 2000

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@article{5efa3aa7b6a54d9f82727db5cfc69ae6,

title = "ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique",

abstract = "A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output, and power pads have been fabricated and verified in a 0.18-μm salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by this substrate-triggered technique.",

author = "Ming-Dou Ker and Chen, {T. Y.} and Chung-Yu Wu",

year = "2000",

month = apr,

language = "English",

volume = "626",

pages = "IV754--IV757",

journal = "Materials Research Society Symposium - Proceedings",

issn = "0272-9172",

publisher = "Materials Research Society",

note = "Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications ; Conference date: 24-04-2000 Through 27-04-2000",

}

TY - JOUR

T1 - ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique

AU - Ker, Ming-Dou

AU - Chen, T. Y.

AU - Wu, Chung-Yu

PY - 2000/4

Y1 - 2000/4

N2 - A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output, and power pads have been fabricated and verified in a 0.18-μm salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by this substrate-triggered technique.

AB - A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output, and power pads have been fabricated and verified in a 0.18-μm salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by this substrate-triggered technique.

UR - http://www.scopus.com/inward/record.url?scp=0035030901&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:0035030901

SN - 0272-9172

VL - 626

SP - IV754-IV757

JO - Materials Research Society Symposium - Proceedings

JF - Materials Research Society Symposium - Proceedings

M1 - 922347

T2 - Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications

Y2 - 24 April 2000 through 27 April 2000

ER -

ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique

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