TY - JOUR
T1 - ESD protection design in a 0.18-μm salicide CMOS technology by using substrate-triggered technique
AU - Ker, Ming-Dou
AU - Chen, T. Y.
AU - Wu, Chung-Yu
PY - 2000/4
Y1 - 2000/4
N2 - A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output, and power pads have been fabricated and verified in a 0.18-μm salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by this substrate-triggered technique.
AB - A novel substrate-triggered technique, as comparing to the traditional gate-driven technique, is proposed to effectively improve ESD (electrostatic discharge) robustness of IC products. The on-chip ESD protection circuits designed with the substrate-triggered technique for input, output, and power pads have been fabricated and verified in a 0.18-μm salicide CMOS process. The HBM ESD level of the ESD protection NMOS with a W/L of 300μm/0.3μm can be improved from the original 0.8kV to become 3.3kV by this substrate-triggered technique.
UR - http://www.scopus.com/inward/record.url?scp=0035030901&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0035030901
SN - 0272-9172
VL - 626
SP - IV754-IV757
JO - Materials Research Society Symposium - Proceedings
JF - Materials Research Society Symposium - Proceedings
M1 - 922347
T2 - Thermoelectric Materials 2000-The Next Generation Materials for Small-Scale Refrigeration and Power Generation Applications
Y2 - 24 April 2000 through 27 April 2000
ER -