ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique

Ming-Dou Ker, Hsin Chyh Hsu

    研究成果: Conference contribution同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    A substrate-triggered technique is proposed to improve ESD protection efficiency of the stacked-NMOS device in a mixed-voltage I/O circuit. The substrate-triggered technique can further lower the trigger voltage of the stacked-NMOS device, to ensure effective ESD protection for the mixed-voltage I/O circuit. The proposed ESD protection circuit, with the substrate-triggered technique, for a 2.5 V/3.3 V tolerant mixed-voltage I/O circuit has been fabricated and verified in a 0.25 μm salicided CMOS process. Experimental results have confirmed that the HBM ESD robustness of the mixed-voltage I/O circuit can be increased ∼60% by this substrate-triggered design.

    原文English
    主出版物標題Proceedings - IEEE International SOC Conference, SOCC 2003
    編輯Dong S. Ha, Richard Auletta, John Chickanosky
    發行者Institute of Electrical and Electronics Engineers Inc.
    頁面219-222
    頁數4
    ISBN(電子)0780381823, 9780780381827
    DOIs
    出版狀態Published - 1 1月 2003
    事件IEEE International SOC Conference, SOCC 2003 - Portland, United States
    持續時間: 17 9月 200320 9月 2003

    出版系列

    名字Proceedings - IEEE International SOC Conference, SOCC 2003

    Conference

    ConferenceIEEE International SOC Conference, SOCC 2003
    國家/地區United States
    城市Portland
    期間17/09/0320/09/03

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