ESD protection design for mixed-voltage I/O interfaces - Overview

Ming Dou Ker*, Kun Hsien Lin

*此作品的通信作者

    研究成果: Conference contribution同行評審

    1 引文 斯高帕斯(Scopus)

    摘要

    Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-a-chip (SOC) implementation in nanoscale CMOS processes. This paper presents an overview on the design concept and circuit implementations of the ESD protection designs for mixed-voltage I/O interfaces without using the additional thick gate-oxide process. The ESD design constraints in mixed-voltage I/O interfaces, the classification, and analysis of ESD protection designs for mixed-voltage I/O interfaces are presented and discussed.

    原文English
    主出版物標題2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
    發行者Institute of Electrical and Electronics Engineers Inc.
    頁面493-498
    頁數6
    ISBN(列印)0780393392, 9780780393394
    DOIs
    出版狀態Published - 1 1月 2005
    事件2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC - Howloon, Hong Kong
    持續時間: 19 12月 200521 12月 2005

    出版系列

    名字2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC

    Conference

    Conference2005 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC
    國家/地區Hong Kong
    城市Howloon
    期間19/12/0521/12/05

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