ESD protection design for high-speed I/O interface of Stub series Terminated Logic (SSTL) in a 0.25-μm salicided CMOS process
Ming-Dou Ker*, Che Hao Chuang
*此作品的通信作者
研究成果: Paper › 同行評審
4
引文
斯高帕斯(Scopus)