ESD protection design for high-speed I/O interface of Stub series Terminated Logic (SSTL) in a 0.25-μm salicided CMOS process

Ming-Dou Ker*, Che Hao Chuang

*此作品的通信作者

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    4 引文 斯高帕斯(Scopus)

    摘要

    ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) is proposed. The SSTL I/O buffer with the proposed ESD protection design, which is designed to operate with a clock of 400MHz, has been fabricated and verified in a 0.25-μm salicided CMOS process. The human-body-model (HBM) and machine-model (MM) ESD levels of this SSTL I/O buffer can be greater than 8kV and 750V, respectively. Based on the excellent ESD performance, one set of area-efficient I/O cell library for SSTL in 1.8-V applications with this ESD protection design has been built up in a 0.25-μm salicided CMOS process.

    原文English
    頁面217-220
    頁數4
    DOIs
    出版狀態Published - 1 12月 2004
    事件Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , 台灣
    持續時間: 5 7月 20048 7月 2004

    Conference

    ConferenceProceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004
    國家/地區台灣
    期間5/07/048/07/04

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