摘要
ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) is proposed. The SSTL I/O buffer with the proposed ESD protection design, which is designed to operate with a clock of 400MHz, has been fabricated and verified in a 0.25-μm salicided CMOS process. The human-body-model (HBM) and machine-model (MM) ESD levels of this SSTL I/O buffer can be greater than 8kV and 750V, respectively. Based on the excellent ESD performance, one set of area-efficient I/O cell library for SSTL in 1.8-V applications with this ESD protection design has been built up in a 0.25-μm salicided CMOS process.
原文 | English |
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頁面 | 217-220 |
頁數 | 4 |
DOIs | |
出版狀態 | Published - 1 12月 2004 |
事件 | Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 - , 台灣 持續時間: 5 7月 2004 → 8 7月 2004 |
Conference
Conference | Proceedings of the 11th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2004 |
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國家/地區 | 台灣 |
期間 | 5/07/04 → 8/07/04 |