@inproceedings{0559e55d2bc1435daa6c6e782fc2686a,
title = "ESD protection design for high-speed applications in CMOS technology",
abstract = "To prevent from electrostatic discharge (ESD) damages, the ESD protection design must be added on chip. The ESD protection design with low parasitic capacitance is needed for high-speed applications. In this work, an ESD protection design realized by stacked diodes with embedded siliconcontrolled rectifier was proposed. Verified in silicon chip, the proposed ESD protection design with lower parasitic capacitance and higher ESD robustness was more suitable for high-speed ESD protection in CMOS technology.",
author = "Chen, {Jie Ting} and Lin, {Chun Yu} and Chang, {Rong Kun} and Ker, {Ming Dou} and Tzeng, {Tzu Chien} and Lin, {Tzu Chiang}",
year = "2016",
month = jul,
day = "2",
doi = "10.1109/MWSCAS.2016.7870016",
language = "English",
series = "Midwest Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2016 IEEE 59th International Midwest Symposium on Circuits and Systems, MWSCAS 2016",
address = "United States",
note = "59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016 ; Conference date: 16-10-2016 Through 19-10-2016",
}