ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process

Yuan Wen Hsiao; Ming-Dou Ker; Po Yen Chiu; Chun Huang; Yuh Kuang Tseng

doi:10.1109/SOCC.2007.4545474

ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process

Yuan Wen Hsiao^*, Ming-Dou Ker, Po Yen Chiu, Chun Huang, Yuh Kuang Tseng

^*此作品的通信作者

研究成果: Conference contribution › 同行評審

2 引文斯高帕斯（Scopus）

摘要

The electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interfaces in a 130-nm CMOS process is proposed in this paper. First, the ESD protection devices were designed and fabricated to evaluate their ESD robustness and the parasitic effects in giga-hertz frequency band. With the knowledge on the dependence of device dimensions on ESD robustness and the parasitic capacitance, the ESD protection circuit for high-speed I/O interfaces was designed with minimum degradation on high-speed circuit performance but satisfactory high ESD robustness.

原文	English
主出版物標題	Proceedings - 20th Anniversary IEEE International SOC Conference
頁面	277-280
頁數	4
DOIs	https://doi.org/10.1109/SOCC.2007.4545474
出版狀態	Published - 1 12月 2007
事件	20th Anniversary IEEE International SOC Conference - Hsinchu, Taiwan 持續時間: 26 9月 2007 → 29 9月 2007

出版系列

名字	Proceedings - 20th Anniversary IEEE International SOC Conference

Conference

Conference	20th Anniversary IEEE International SOC Conference
國家/地區	Taiwan
城市	Hsinchu
期間	26/09/07 → 29/09/07

存取文件

10.1109/SOCC.2007.4545474

其它文件與鏈接

Link to publication in Scopus

引用此

@inproceedings{cf6958fc4d404fc88a84e6f58f185017,

title = "ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process",

abstract = "The electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interfaces in a 130-nm CMOS process is proposed in this paper. First, the ESD protection devices were designed and fabricated to evaluate their ESD robustness and the parasitic effects in giga-hertz frequency band. With the knowledge on the dependence of device dimensions on ESD robustness and the parasitic capacitance, the ESD protection circuit for high-speed I/O interfaces was designed with minimum degradation on high-speed circuit performance but satisfactory high ESD robustness.",

author = "Hsiao, {Yuan Wen} and Ming-Dou Ker and Chiu, {Po Yen} and Chun Huang and Tseng, {Yuh Kuang}",

year = "2007",

month = dec,

day = "1",

doi = "10.1109/SOCC.2007.4545474",

language = "English",

isbn = "9781424415922",

series = "Proceedings - 20th Anniversary IEEE International SOC Conference",

pages = "277--280",

booktitle = "Proceedings - 20th Anniversary IEEE International SOC Conference",

note = "20th Anniversary IEEE International SOC Conference ; Conference date: 26-09-2007 Through 29-09-2007",

}

Hsiao, YW, Ker, M-D, Chiu, PY, Huang, C & Tseng, YK 2007, ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process. 於 Proceedings - 20th Anniversary IEEE International SOC Conference., 4545474, Proceedings - 20th Anniversary IEEE International SOC Conference, 頁 277-280, 20th Anniversary IEEE International SOC Conference, Hsinchu, Taiwan, 26/09/07. https://doi.org/10.1109/SOCC.2007.4545474

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AU - Hsiao, Yuan Wen

AU - Ker, Ming-Dou

AU - Chiu, Po Yen

AU - Huang, Chun

AU - Tseng, Yuh Kuang

PY - 2007/12/1

Y1 - 2007/12/1

N2 - The electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interfaces in a 130-nm CMOS process is proposed in this paper. First, the ESD protection devices were designed and fabricated to evaluate their ESD robustness and the parasitic effects in giga-hertz frequency band. With the knowledge on the dependence of device dimensions on ESD robustness and the parasitic capacitance, the ESD protection circuit for high-speed I/O interfaces was designed with minimum degradation on high-speed circuit performance but satisfactory high ESD robustness.

AB - The electrostatic discharge (ESD) protection design for high-speed input/output (I/O) interfaces in a 130-nm CMOS process is proposed in this paper. First, the ESD protection devices were designed and fabricated to evaluate their ESD robustness and the parasitic effects in giga-hertz frequency band. With the knowledge on the dependence of device dimensions on ESD robustness and the parasitic capacitance, the ESD protection circuit for high-speed I/O interfaces was designed with minimum degradation on high-speed circuit performance but satisfactory high ESD robustness.

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U2 - 10.1109/SOCC.2007.4545474

DO - 10.1109/SOCC.2007.4545474

M3 - Conference contribution

AN - SCOPUS:51049119382

SN - 9781424415922

T3 - Proceedings - 20th Anniversary IEEE International SOC Conference

SP - 277

EP - 280

BT - Proceedings - 20th Anniversary IEEE International SOC Conference

T2 - 20th Anniversary IEEE International SOC Conference

Y2 - 26 September 2007 through 29 September 2007

ER -

ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process

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