@inproceedings{f6e6c2ff430643bba47ce6358005df40,
title = "ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces",
abstract = "With consideration on the gate-oxide reliability, the new ESD protection design with ESD bus for 1.2/2.5-V mixed-voltage I/O interfaces is reported by using the new proposed high-voltage-tolerant power-rail electrostatic discharge (ESD) clamp circuit. This proposed power-rail ESD clamp circuit with only 1.2-V low-voltage NMOS/ PMOS devices can be operated under the 2.5-V input conditions without suffering the gate-oxide reliability issue. The experimental results in a 0.13-μm CMOS process have confirmed that the proposed power-rail ESD clamp circuit has high human-body-model (HBM) and machine-model (MM) ESD robustness and fast turn-on speed. The proposed power-rail ESD clamp circuit is an excellent ESD protection solution to the mixed-voltage I/O interfaces.",
author = "Chang, {Wei Jen} and Ming-Dou Ker",
year = "2006",
month = dec,
day = "1",
doi = "10.1109/RME.2006.1689957",
language = "English",
isbn = "1424401577",
series = "PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics - Proceedings",
pages = "305--308",
booktitle = "PRIME 2006",
note = "PRIME 2006: 2nd Conference on Ph.D. Research in MicroElectronics and Electronics ; Conference date: 12-06-2006 Through 15-06-2006",
}