@inproceedings{54143908c8a5478c9f0dba14688e55e6,
title = "ESD protection design and verification in a 0.35-μm CMOS ASIC library",
abstract = "In this paper, ESD protection design on the I/O cells of a CMOS ASIC library in a 0.35-μm silicide CMOS technology is proposed with practical verification on the experimental testchips. The whole-chip ESD robustness of such I/O cells in the 0.35-μm CMOS ASIC library has been practically investigated by four 40-pins testchips with internal core circuits. By applying the efficient VDD-to-VSS ESD clamp circuit and the ESD-related process modifications, the whole-chip human-body-model (machine-model) ESD level of this 0.35-μm CMOS ASIC library can be greater than 6 kV (1 kV). By including the clamp devices into the input stage, the charged-device-model ESD level of the input pin can be greater than 2 kV.",
author = "Ming-Dou Ker and Jiang, {Hsin Chin} and Peng, {Jeng Jie}",
year = "1999",
month = jan,
day = "1",
doi = "10.1109/ASIC.1999.806516",
language = "English",
series = "Proceedings - 12th Annual IEEE International ASIC/SOC Conference",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "262--266",
booktitle = "Proceedings - 12th Annual IEEE International ASIC/SOC Conference",
address = "United States",
note = "12th Annual IEEE International ASIC/SOC Conference ; Conference date: 15-09-1999 Through 18-09-1999",
}