TY - GEN
T1 - ESD-induced latchup-like failure in a touch panel control IC
AU - Ker, Ming-Dou
AU - Chiu, Po Yen
AU - Shieh, Wuu Trong
AU - Wang, Chun Chi
PY - 2017/10/5
Y1 - 2017/10/5
N2 - With on-chip ESD protection design, the I/O pins of a touch panel control IC can pass the chip-level ESD tests of HBM 4kV and MM 400V. However, such a touch panel control IC mounted onto a display panel suffered the latchup-like failure after the system-level ESD zapping in the air-discharge mode. Some high-voltage power pin began to generate a large leakage current after the system-level ESD test, which demonstrated a symptom of latchup failure. By failure analyses with TLP-measurement, EMMI, and SEM, the root cause has been found on the power-rail ESD clamp circuit of the high-voltage power pin. The holding voltage of the power-rail ESD clamp circuit in the high-voltage power pin, that was lower than its normal operating voltage, caused such a latchup-like failure. Some modified solutions to rescue this latchup-like failure in the touch panel control IC are presented.
AB - With on-chip ESD protection design, the I/O pins of a touch panel control IC can pass the chip-level ESD tests of HBM 4kV and MM 400V. However, such a touch panel control IC mounted onto a display panel suffered the latchup-like failure after the system-level ESD zapping in the air-discharge mode. Some high-voltage power pin began to generate a large leakage current after the system-level ESD test, which demonstrated a symptom of latchup failure. By failure analyses with TLP-measurement, EMMI, and SEM, the root cause has been found on the power-rail ESD clamp circuit of the high-voltage power pin. The holding voltage of the power-rail ESD clamp circuit in the high-voltage power pin, that was lower than its normal operating voltage, caused such a latchup-like failure. Some modified solutions to rescue this latchup-like failure in the touch panel control IC are presented.
UR - http://www.scopus.com/inward/record.url?scp=85045075195&partnerID=8YFLogxK
U2 - 10.1109/IPFA.2017.8060061
DO - 10.1109/IPFA.2017.8060061
M3 - Conference contribution
AN - SCOPUS:85045075195
T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
SP - 1
EP - 5
BT - 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2017
Y2 - 4 July 2017 through 7 July 2017
ER -