ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

Ming-Dou Ker; C. H. Chuang

doi:10.1109/IPFA.2001.941461

ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

Ming-Dou Ker^*, C. H. Chuang

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研究成果: Paper › 同行評審

23 引文斯高帕斯（Scopus）

摘要

The second breakdown current (It2) and ESD level of NMOS devices and diodes with different ESD implantations for on-chip ESD protection were verified in a 0.18-μm salicide bulk CMOS technology. The significant improvement was observed when the NMOS is fabricated with boron or arsenic ESD implantations.

原文	English
頁面	85-90
頁數	6
DOIs	https://doi.org/10.1109/IPFA.2001.941461
出版狀態	Published - 13 7月 2001
事件	8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) - Singapure, 新加坡持續時間: 9 7月 2001 → 13 7月 2001

Conference

Conference	8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001)
國家/地區	新加坡
城市	Singapure
期間	9/07/01 → 13/07/01

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10.1109/IPFA.2001.941461

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@conference{b61f8aaf905a4e4b9c3556c4c9a5b963,

title = "ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration",

abstract = "The second breakdown current (It2) and ESD level of NMOS devices and diodes with different ESD implantations for on-chip ESD protection were verified in a 0.18-μm salicide bulk CMOS technology. The significant improvement was observed when the NMOS is fabricated with boron or arsenic ESD implantations.",

author = "Ming-Dou Ker and Chuang, {C. H.}",

year = "2001",

month = jul,

day = "13",

doi = "10.1109/IPFA.2001.941461",

language = "English",

pages = "85--90",

note = "8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) ; Conference date: 09-07-2001 Through 13-07-2001",

}

TY - CONF

T1 - ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

AU - Ker, Ming-Dou

AU - Chuang, C. H.

PY - 2001/7/13

Y1 - 2001/7/13

N2 - The second breakdown current (It2) and ESD level of NMOS devices and diodes with different ESD implantations for on-chip ESD protection were verified in a 0.18-μm salicide bulk CMOS technology. The significant improvement was observed when the NMOS is fabricated with boron or arsenic ESD implantations.

AB - The second breakdown current (It2) and ESD level of NMOS devices and diodes with different ESD implantations for on-chip ESD protection were verified in a 0.18-μm salicide bulk CMOS technology. The significant improvement was observed when the NMOS is fabricated with boron or arsenic ESD implantations.

UR - http://www.scopus.com/inward/record.url?scp=0034823704&partnerID=8YFLogxK

U2 - 10.1109/IPFA.2001.941461

DO - 10.1109/IPFA.2001.941461

M3 - Paper

AN - SCOPUS:0034823704

SP - 85

EP - 90

T2 - 8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001)

Y2 - 9 July 2001 through 13 July 2001

ER -

ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

摘要

Conference

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