ESD implantations in 0.18-μm salicided CMOS technology for on-chip ESD protection with layout consideration

Ming-Dou Ker*, C. H. Chuang

*此作品的通信作者

    研究成果: Paper同行評審

    22 引文 斯高帕斯(Scopus)

    摘要

    The second breakdown current (It2) and ESD level of NMOS devices and diodes with different ESD implantations for on-chip ESD protection were verified in a 0.18-μm salicide bulk CMOS technology. The significant improvement was observed when the NMOS is fabricated with boron or arsenic ESD implantations.

    原文English
    頁面85-90
    頁數6
    DOIs
    出版狀態Published - 13 7月 2001
    事件8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001) - Singapure, Singapore
    持續時間: 9 7月 200113 7月 2001

    Conference

    Conference8th International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2001)
    國家/地區Singapore
    城市Singapure
    期間9/07/0113/07/01

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