Error Diluting: Exploiting 3-D nand Flash Process Variation for Efficient Read on LDPC-Based SSDs

Keyphrases

• Process Variation 100%
• Low-density Parity-check Codes 100%
• 3D NAND 100%
• 3D NAND Flash 100%
• Flash Process 100%
• Bit Error 75%
• Error-prone 50%
• Cellular Structure 25%
• In(III) 25%
• Error Correction 25%
• Bit Error Rate 25%
• Upper Layer 25%
• Lower Layer 25%
• Bit Storage 25%
• Storage Density 25%
• Time Overhead 25%
• Bit Data 25%
• Error Correction Codes 25%
• Multi-chip 25%
• Rate Variation 25%
• Read Throughput 25%
• High Time 25%
• Read Latency 25%
• Vertical Layer 25%
• Large Capacity 25%
• Cylindrical Cell 25%

Engineering

• Bit Error 100%
• Flash Process 100%
• Process Variation 100%
• Bit Input 66%
• Input Information 66%
• Experimental Result 33%
• Error Correction 33%
• Bit Error Rate 33%
• Data Bit 33%
• Error-correcting code 33%

Computer Science

• Process Variation 100%
• Input Information 100%
• Experimental Result 50%
• Error Correction 50%
• Error-correcting code 50%