Error Diluting: Exploiting 3-D nand Flash Process Variation for Efficient Read on LDPC-Based SSDs

Kong Kiat Yong, Li Pin Chang*

*此作品的通信作者

研究成果: Article同行評審

13 引文 斯高帕斯(Scopus)

摘要

3-D NAND flash has become the mainstream in modern SSD designs because it offers superior bit storage density. However, while enjoying the large capacity, 3-D NAND flash is highly prone to bit errors due to its cylindrical cell structure. Modern SSDs employ the low-density parity-check (LDPC) error-correcting code to manage bit errors in 3-D NAND flash. Strong LDPC error correction is subject to a high time overhead, because it may require many sensing levels on read to obtain sufficiently confident bit input information. By exploiting the bit-error rate variation among vertical layers of 3-D NAND flash, we propose diluting bit errors of cells at error-prone, lower layers by mixing them with bit data of cells from reliable, upper layers. Cells at reliable layers provide highly confident bit input information that helps reduce the number of sensing levels on cell at error-prone layers. Our experimental results showed that the proposed approach improved the read throughput by 29% and reduced the read latency by 43% compared with a conventional multichip SSD design.

原文English
文章編號9211439
頁(從 - 到)3467-3478
頁數12
期刊IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
39
發行號11
DOIs
出版狀態Published - 11月 2020

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