Enhancing utilization of simd-like accelerator for sparse convolutional neural networks

Bo-Cheng Lai*, Jyun Wei Pan, Chien Yu Lin


研究成果: Article同行評審

11 引文 斯高帕斯(Scopus)


Although the existing single-instruction-multiple-data-like (SIMD) accelerators can handle the compressed format of sparse convolutional neural networks, the sparse and irregular distributions of nonzero elements cause low utilization of multipliers in a processing engine (PE) and imbalanced computation between PEs. This brief addresses the above issues by proposing a data screening and task mapping (DSTM) accelerator which integrates a series of techniques, including software refinement and hardware modules. An efficient indexing module is introduced to identify the effectual computation pairs and skip unnecessary computation in a fine-grained manner. The intra-PE load imbalance is alleviated with weight data rearrangement. An effective task sharing mechanism further balances the computation between PEs. When compared with the state-of-the-art SIMD-like accelerator, the proposed DSTM enhances the average PE utilization by 3.5\times. The overall processing throughput is 59.7% higher than the previous design.

頁(從 - 到)1218-1222
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
出版狀態Published - 1 5月 2019


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