Enhancing Data Reuse in Cache Contention Aware Thread Scheduling on GPGPU

Chin Fu Lu, Hsien Kai Kuo, Bo-Cheng Lai

研究成果: Conference contribution同行評審

摘要

GPGPUs have been widely adopted as throughput processing platforms for modern big-data and cloud computing. Attaining a high performance design on a GPGPU requires careful tradeoffs among various design concerns. Data reuse, cache contention, and thread level parallelism, have been demonstrated as three imperative performance factors for a GPGPU. The correlated performance impacts of these factors pose non-Trivial concerns when scheduling threads on GPGPUs. This paper proposes a three-staged scheduling scheme to coschedule the threads with consideration of the three factors. The experiment results on a set of irregular parallel applications, when compared with previous approaches, have demonstrated up to 70% execution time improvement.

原文English
主出版物標題Proceedings - 2016 10th International Conference on Complex, Intelligent, and Software Intensive Systems, CISIS 2016
編輯Leonard Barolli, Fatos Xhafa, Makoto Ikeda
發行者Institute of Electrical and Electronics Engineers Inc.
頁面351-356
頁數6
ISBN(電子)9781509009879
DOIs
出版狀態Published - 19 12月 2016
事件10th International Conference on Complex, Intelligent, and Software Intensive Systems, CISIS 2016 - Fukuoka, Japan
持續時間: 6 7月 20168 7月 2016

出版系列

名字Proceedings - 2016 10th International Conference on Complex, Intelligent, and Software Intensive Systems, CISIS 2016

Conference

Conference10th International Conference on Complex, Intelligent, and Software Intensive Systems, CISIS 2016
國家/地區Japan
城市Fukuoka
期間6/07/168/07/16

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