摘要
In this work an enhanced electrically erasable programmable read-only memory (EEPROM) device comprised of twin low-temperature poly-Si thin-film transistors (TFTs) was fabricated for potential application to system-on-panel technology. Also, two kinds of memory devices with different overlap areas were developed to investigate the gate-coupling effect. The memory window of 4.8 and 4 V can be obtained at a programming voltage of 18 V, separately, for the fully overlapped EEPROM and the one with a 1 μm length overlap between the gate and source/drain. The excellent memory characteristics of the fully overlapped TFT EEPROM cell are attributed to the enhanced gate-coupling ratio by maximizing the overlap coverage between the gate electrode and the source/drain regions.
| 原文 | English |
|---|---|
| 頁（從 - 到） | J89-J91 |
| 頁數 | 3 |
| 期刊 | Electrochemical and Solid-State Letters |
| 卷 | 10 |
| 發行號 | 8 |
| DOIs | |
| 出版狀態 | Published - 1月 2007 |