Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition

Shang Lin Wu; Po-Tsang Huang; Teng Chieh Huang; Kuan-Neng Chen; Jin-Chern Chiou; Kuo Hua Chen; Chi Tsung Chiu; Ho Ming Tong; Ching Te Chuang; Wei Hwang

doi:10.1109/VLSI-DAT.2014.6834893

Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition

Shang Lin Wu, Po-Tsang Huang, Teng Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo Hua Chen, Chi Tsung Chiu, Ho Ming Tong, Ching Te Chuang, Wei Hwang

研究成果: Conference contribution › 同行評審

4 引文斯高帕斯（Scopus）

摘要

In this paper, an energy-efficient and low-noise 16-channel analog front-end (AFE) circuitry is proposed for acquisition of electrophysiological signals. This fully integrated front-end circuit comprises two differential difference amplifiers (DDAs) and DC offset rejection components. Additionally, the DDA is designed using a double input G_m-stage and a class-AB output for achieving high common-mode rejection ratio (CMRR), low-noise and energy efficiency. The 16-channel AFE with analog-to-digital converters (ADCs) is implemented in TSMC 0.18μm CMOS process. The measurement results show that the AFE can realize 60.3dB gain with only 20.67μW for each channel. The bandwidth of the AFE is from 2.32Hz to 6.61kHz. Furthermore, the total input referred noise and noise efficiency factor (NEF) are 0.826μV_rms and 2.78 only within the target frequency range of 0.1Hz to kHz, respectively.

原文	English
主出版物標題	Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
發行者	IEEE Computer Society
ISBN（列印）	9781479927760
DOIs	https://doi.org/10.1109/VLSI-DAT.2014.6834893
出版狀態	Published - 1 1月 2014
事件	2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 - Hsinchu, Taiwan 持續時間: 28 4月 2014 → 30 4月 2014

出版系列

名字	Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

Conference

Conference	2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014
國家/地區	Taiwan
城市	Hsinchu
期間	28/04/14 → 30/04/14

UN SDG

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存取文件

10.1109/VLSI-DAT.2014.6834893

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Link to publication in Scopus

引用此

Wu, S. L., Huang, P-T., Huang, T. C., Chen, K-N., Chiou, J-C., Chen, K. H., Chiu, C. T., Tong, H. M., Chuang, C. T., & Hwang, W. (2014). Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. 於 Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014 [6834893] (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). IEEE Computer Society. https://doi.org/10.1109/VLSI-DAT.2014.6834893

Wu, Shang Lin ; Huang, Po-Tsang ; Huang, Teng Chieh 等. / Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 2014. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

@inproceedings{87c13d9ddc604de4991931da43a867ad,

title = "Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition",

abstract = "In this paper, an energy-efficient and low-noise 16-channel analog front-end (AFE) circuitry is proposed for acquisition of electrophysiological signals. This fully integrated front-end circuit comprises two differential difference amplifiers (DDAs) and DC offset rejection components. Additionally, the DDA is designed using a double input Gm-stage and a class-AB output for achieving high common-mode rejection ratio (CMRR), low-noise and energy efficiency. The 16-channel AFE with analog-to-digital converters (ADCs) is implemented in TSMC 0.18μm CMOS process. The measurement results show that the AFE can realize 60.3dB gain with only 20.67μW for each channel. The bandwidth of the AFE is from 2.32Hz to 6.61kHz. Furthermore, the total input referred noise and noise efficiency factor (NEF) are 0.826μVrms and 2.78 only within the target frequency range of 0.1Hz to kHz, respectively.",

author = "Wu, {Shang Lin} and Po-Tsang Huang and Huang, {Teng Chieh} and Kuan-Neng Chen and Jin-Chern Chiou and Chen, {Kuo Hua} and Chiu, {Chi Tsung} and Tong, {Ho Ming} and Chuang, {Ching Te} and Wei Hwang",

year = "2014",

month = jan,

day = "1",

doi = "10.1109/VLSI-DAT.2014.6834893",

language = "English",

isbn = "9781479927760",

series = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",

publisher = "IEEE Computer Society",

booktitle = "Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014",

address = "United States",

note = "null ; Conference date: 28-04-2014 Through 30-04-2014",

}

Wu, SL, Huang, P-T, Huang, TC, Chen, K-N , Chiou, J-C, Chen, KH, Chiu, CT, Tong, HM, Chuang, CT & Hwang, W 2014, Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. 於 Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014., 6834893, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, IEEE Computer Society, 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014, Hsinchu, Taiwan, 28/04/14. https://doi.org/10.1109/VLSI-DAT.2014.6834893

Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. / Wu, Shang Lin; Huang, Po-Tsang; Huang, Teng Chieh 等.

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society, 2014. 6834893 (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014).

研究成果: Conference contribution › 同行評審

TY - GEN

T1 - Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition

AU - Wu, Shang Lin

AU - Huang, Po-Tsang

AU - Huang, Teng Chieh

AU - Chen, Kuan-Neng

AU - Chiou, Jin-Chern

AU - Chen, Kuo Hua

AU - Chiu, Chi Tsung

AU - Tong, Ho Ming

AU - Chuang, Ching Te

AU - Hwang, Wei

PY - 2014/1/1

Y1 - 2014/1/1

N2 - In this paper, an energy-efficient and low-noise 16-channel analog front-end (AFE) circuitry is proposed for acquisition of electrophysiological signals. This fully integrated front-end circuit comprises two differential difference amplifiers (DDAs) and DC offset rejection components. Additionally, the DDA is designed using a double input Gm-stage and a class-AB output for achieving high common-mode rejection ratio (CMRR), low-noise and energy efficiency. The 16-channel AFE with analog-to-digital converters (ADCs) is implemented in TSMC 0.18μm CMOS process. The measurement results show that the AFE can realize 60.3dB gain with only 20.67μW for each channel. The bandwidth of the AFE is from 2.32Hz to 6.61kHz. Furthermore, the total input referred noise and noise efficiency factor (NEF) are 0.826μVrms and 2.78 only within the target frequency range of 0.1Hz to kHz, respectively.

AB - In this paper, an energy-efficient and low-noise 16-channel analog front-end (AFE) circuitry is proposed for acquisition of electrophysiological signals. This fully integrated front-end circuit comprises two differential difference amplifiers (DDAs) and DC offset rejection components. Additionally, the DDA is designed using a double input Gm-stage and a class-AB output for achieving high common-mode rejection ratio (CMRR), low-noise and energy efficiency. The 16-channel AFE with analog-to-digital converters (ADCs) is implemented in TSMC 0.18μm CMOS process. The measurement results show that the AFE can realize 60.3dB gain with only 20.67μW for each channel. The bandwidth of the AFE is from 2.32Hz to 6.61kHz. Furthermore, the total input referred noise and noise efficiency factor (NEF) are 0.826μVrms and 2.78 only within the target frequency range of 0.1Hz to kHz, respectively.

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U2 - 10.1109/VLSI-DAT.2014.6834893

DO - 10.1109/VLSI-DAT.2014.6834893

M3 - Conference contribution

AN - SCOPUS:84903957239

SN - 9781479927760

T3 - Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

BT - Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014

PB - IEEE Computer Society

Y2 - 28 April 2014 through 30 April 2014

ER -

Wu SL, Huang P-T, Huang TC, Chen K-N , Chiou J-C, Chen KH 等. Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. 於 Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014. IEEE Computer Society. 2014. 6834893. (Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2014). doi: 10.1109/VLSI-DAT.2014.6834893

Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition

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