TY - GEN
T1 - Energy efficient CNN inference accelerator using fast fourier transform
AU - Chung, Ya Chin
AU - Cheng, Po Hsiang
AU - Liu, Chih Wei
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/4
Y1 - 2019/4
N2 - We use FFT-based convolution in frequency domain to reduce computational complexity in CNNs. The properties of conjugate symmetry and down-sampling is adopted to further reduce complexity. By eliminating filter weights in CNNs that can save computational requirement but lead to accuracy loss. The simulation result reveals that eliminating filter weights in frequency domain is more accurate than that in time domain. With the proposed design synthesized by TSMC 90 nm CMOS technology, the total latency, power and energy are considerably competitive. As a result, our FFT-based CNN accelerator is energy-efficient.
AB - We use FFT-based convolution in frequency domain to reduce computational complexity in CNNs. The properties of conjugate symmetry and down-sampling is adopted to further reduce complexity. By eliminating filter weights in CNNs that can save computational requirement but lead to accuracy loss. The simulation result reveals that eliminating filter weights in frequency domain is more accurate than that in time domain. With the proposed design synthesized by TSMC 90 nm CMOS technology, the total latency, power and energy are considerably competitive. As a result, our FFT-based CNN accelerator is energy-efficient.
UR - http://www.scopus.com/inward/record.url?scp=85068618897&partnerID=8YFLogxK
U2 - 10.1109/VLSI-DAT.2019.8741633
DO - 10.1109/VLSI-DAT.2019.8741633
M3 - Conference contribution
AN - SCOPUS:85068618897
T3 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
BT - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
Y2 - 22 April 2019 through 25 April 2019
ER -