Embedded TCP/IP Controller for a RISC-V SoC

Chun Jen Tsai, Yi De Lee

研究成果: Conference contribution同行評審

2 引文 斯高帕斯(Scopus)

摘要

In this paper, we present the design of an open-source RISC-V application processor with an embedded TCP/IP network module. Traditionally, the TCP/IP stack is a software layer of the OS kernel due to its complex control behavior. However, previous studies show that a hardwired logic can perform the TCP/IP control algorithms much more efficiently than a software implementation. However, to allow a processor to invoke a hardware TCP/IP logic efficiently is not a trivial task. This paper proposes an efficient interface logic between the processor core and the hardware TCP/IP stack through user-defined RISC-V instructions. The proposed architecture is implemented and verified on a Xilinx FPGA development board. Experimental results show that the average end-to-end packet delay can be reduced by up to 99% using the proposed network module when compared against the software network stack under the FreeRTOS real-time operating system. Therefore, the proposed architecture can be very useful for deeply-embedded IOT devices where a low-power processor can be used to handle low-latency high throughput IP packet transmissions.

原文English
主出版物標題Proceedings of the 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022
發行者IEEE Computer Society
ISBN(電子)9781665490054
DOIs
出版狀態Published - 2022
事件30th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2022 - Patras, Greece
持續時間: 3 10月 20225 10月 2022

出版系列

名字IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC
2022-October
ISSN(列印)2324-8432
ISSN(電子)2324-8440

Conference

Conference30th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2022
國家/地區Greece
城市Patras
期間3/10/225/10/22

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