Electrostatic discharge protection design for high-voltage programming pin in fully-silicided CMOS ICs

For integrated circuits (ICs) with voltage programming pin (V_PP pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the V_PP pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to VDD cannot be applied to such V_PP pin. In this work, a new ESD protection design is proposed to improve ESD robustness of V_PP pin with the consideration of the mistriggering issue when VPP programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.