Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed I/O interface circuits

Ming-Dou Ker, Hsin Chyh Hsu, Jeng Jie Peng

    研究成果: Conference contribution同行評審

    2 引文 斯高帕斯(Scopus)

    摘要

    A novel electrostatic discharge (ESD) implantation method is proposed to significantly improve machine-model (MM) ESD robustness of NMOS device in stacked configuration (stacked NMOS). By using this ESD implantation method, the ESD current is discharged far away from the surface channel of NMOS, therefore the stacked NMOS in the mixed-voltage I/O interface can sustain a much higher ESD level, especially under the MM ESD stress. The MM ESD robustness of the stacked NMOS with a device dimension of W/L=300 μm/0.5 μm for each NMOS has been successfully improved from the original 358 V to become 491 V in a 0.25 μm CMOS process. This ESD implantation method with the n-type impurity is fully process-compatible to general sub-quarter-micron CMOS processes.

    原文English
    主出版物標題Proceedings of the 2003 4th International Symposium on Quality Electronic Design, ISQED 2003
    發行者IEEE Computer Society
    頁面363-368
    頁數6
    ISBN(電子)0769518818
    DOIs
    出版狀態Published - 1 1月 2003
    事件2003 4th International Symposium on Quality Electronic Design, ISQED 2003 - San Jose, United States
    持續時間: 24 3月 200326 3月 2003

    出版系列

    名字Proceedings - International Symposium on Quality Electronic Design, ISQED
    2003-January
    ISSN(列印)1948-3287
    ISSN(電子)1948-3295

    Conference

    Conference2003 4th International Symposium on Quality Electronic Design, ISQED 2003
    國家/地區United States
    城市San Jose
    期間24/03/0326/03/03

    指紋

    深入研究「Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed I/O interface circuits」主題。共同形成了獨特的指紋。

    引用此