Electrical properties of low-temperature-compatible P-channel polycrystalline-silicon TFTs using high-κ gate dielectrics

In this paper, we describe a systematic study of the electrical properties of low-temperature-compatible p-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs) using HfO₂ and HfSiO_χ high-κ gate dielectrics. Because of their larger gate capacitance density, the TFTs containing the high-κ gate dielectrics exhibited superior device performance in terms of higher _on/I_off current ratios, lower subthreshold swings (SSs), and lower threshold voltages (V_th, relative to conventional deposited-SiO₂, albeit with slightly higher OFF-state currents. The TFTs incorporating HfSiO_χ as the gate dielectric had ca. 1.73 times the mobility (μ_FE ) relative to that of the deposited-SiO₂ TFTs; in contrast, the HfO₂ TFTs exhibited inferior mobility. We investigated the mechanism for the mobility degradation in these HfO₂ TFTs. The immunity of the HfSiO_χ TFTs was better than that of the HfO₂ TFTs-in terms of their V_th shift, SS degradation, SS degradation, and drive current deterioration-against negative bias temperature instability stressing. Thus, we believe that HfSiOχ, rather than HfO₂, is a potential candidate for use as a gate-dielectric material in future high-performance poly-Si TFTs.