Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through-Silicon Via

Yi Chieh Tsai; Chia Hsuan Lee; Hsin Chi Chang; Jui Han Liu; Han Wen Hu; Hiroyuki Ito; Young Suk Kim; Takayuki Ohba; Kuan-Neng Chen

doi:10.1109/TED.2021.3082497

Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through-Silicon Via

Yi Chieh Tsai, Chia Hsuan Lee, Hsin Chi Chang, Jui Han Liu, Han Wen Hu, Hiroyuki Ito, Young Suk Kim, Takayuki Ohba, Kuan-Neng Chen

研究成果: Article › 同行評審

11 引文斯高帕斯（Scopus）

摘要

Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, and the new lumped circuit model is proposed to simulate the performance of the structure. Including the actual contact resistance in the model, the integrity of the high-frequency signal can be accurately simulated. For the 12-layer stacked bumpless TSV structure with plasma cleaning at the via bottom, the transmission loss of the signal up to 20 GHz can be lower than 2 dB. High eye height and low jitter at 3.2 Gbps show excellent signal integrity for high bandwidth memory (HBM) applications. In addition, a complete reliability study, including thermal cycling test (TCT), highly accelerated stress test (HAST), and electromigration test, reveals excellent electrical and mechanical properties, indicating that the structure is robust with great potential for 3-D integration.

原文	English
文章編號	9444571
頁（從 - 到）	3520-3525
頁數	6
期刊	IEEE Transactions on Electron Devices
卷	68
發行號	7
DOIs	https://doi.org/10.1109/TED.2021.3082497
出版狀態	Published - 7月 2021

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abstract = "Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, and the new lumped circuit model is proposed to simulate the performance of the structure. Including the actual contact resistance in the model, the integrity of the high-frequency signal can be accurately simulated. For the 12-layer stacked bumpless TSV structure with plasma cleaning at the via bottom, the transmission loss of the signal up to 20 GHz can be lower than 2 dB. High eye height and low jitter at 3.2 Gbps show excellent signal integrity for high bandwidth memory (HBM) applications. In addition, a complete reliability study, including thermal cycling test (TCT), highly accelerated stress test (HAST), and electromigration test, reveals excellent electrical and mechanical properties, indicating that the structure is robust with great potential for 3-D integration.",

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AU - Lee, Chia Hsuan

AU - Chang, Hsin Chi

AU - Liu, Jui Han

AU - Hu, Han Wen

AU - Ito, Hiroyuki

AU - Kim, Young Suk

AU - Ohba, Takayuki

AU - Chen, Kuan-Neng

N1 - Publisher Copyright: IEEE

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KW - 3-D integration

KW - bumpless

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Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through-Silicon Via

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