Efficient write scheme for algorithm-based multi-ported memory

Bo Ya Chen, Bo En Cher, Bo Cheng Lai

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

This paper proposes REMAP+, a novel design that enables efficient write scheme for algorithmic multi-ported memory, and attains better performance with smaller area. REMAP+ applies the banking structure of memory design and implements the remap table with SRAM cells instead of costly registers. In the remap table, REMAP+ only keeps the most significant bit of write addresses to more efficiently utilize the space in the table. The hash write controller is simplified with the first fit algorithm to handle write conflict with shorter latency. REMAP+ is implemented in a pipeline scheme to further increase the processing throughput. For a 3W1R memory with 16K depth, REMAP+ has attained 22% shorter access latency and 31.3% smaller area when compared with the previous design.

原文English
主出版物標題2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781728106557
DOIs
出版狀態Published - 4月 2019
事件2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019 - Hsinchu, Taiwan
持續時間: 22 4月 201925 4月 2019

出版系列

名字2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019

Conference

Conference2019 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019
國家/地區Taiwan
城市Hsinchu
期間22/04/1925/04/19

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