Efficient VLSI architecture for separable 2-D discrete wavelet transform

Wen-Hsiao Peng*, Chen-Yi Lee

*此作品的通信作者

研究成果: Paper同行評審

4 引文 斯高帕斯(Scopus)

摘要

In this paper, we present a VLSI architecture for separable 2-D Discrete Wavelet Transform (DWT). Based on 1-D DWT Recursive Pyramid Algorithm (RPA), a complete 2-D DWT output scheduling scheme is derived. The I/O between memory which stores the intermediate results and DWT core is simplified by `circular coefficients arrangement'. And the concept to store the `partial accumulation sum' of convolution operation in column direction is first proposed in this paper. For the computations of N×N 2-D DWT with filter length L, our architecture spends N2 clock cycles and requires 2NL words in memory size, 4L multipliers, as well as 4L-2 adders. And the number of multipliers and adders can be further reduced to 2L and 2L-1 respectively by sharing positive and negative clock edge. The architecture is suitable for VLSI implementation and various real-time video/image applications.

原文English
頁面754-758
頁數5
DOIs
出版狀態Published - 1 十二月 1999
事件International Conference on Image Processing (ICIP'99) - Kobe, Jpn
持續時間: 24 十月 199928 十月 1999

Conference

ConferenceInternational Conference on Image Processing (ICIP'99)
城市Kobe, Jpn
期間24/10/9928/10/99

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