Efficient systolic architectures for 1-D and 2-D DLMS adaptive digital filters

Lan-Da Van*, Wu Shiung Feng

*此作品的通信作者

研究成果: Paper同行評審

11 引文 斯高帕斯(Scopus)

摘要

In this paper, we propose two efficient systolic architectures for 1-D and 2-D Delay Least-Mean-Square (DLMS) adaptive digital filters. Using our developed architectures, higher convergence rate and Signal-to-Noise Ratio (SNR) than those of the conventional DLMS structure can be obtained without sacrificing the properties of the systolic architecture. Furthermore, the adaptive digital filters operate at the highest throughout due to the new tree-systolic processing element. Besides, based on our proposed optimized rule, one can easily design N th tap and window size N × N systolic adaptive digital filters with the compromise of minimum delay and high regularity under the constraint of the maximum number of tap-connections of the feedback signal.

原文English
頁面399-402
頁數4
DOIs
出版狀態Published - 2000
事件2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems - Tianjin, China
持續時間: 4 12月 20006 12月 2000

Conference

Conference2000 IEEE Asia-Pacific Conference on Circuits and Systems: Electronic Communication Systems
國家/地區China
城市Tianjin
期間4/12/006/12/00

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