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Efficient power-analysis-resistant dual-field elliptic curve cryptographic processor using heterogeneous dual-processing-element architecture
Jen Wei Lee, Szu Chi Chung,
Hsie-Chia Chang
,
Chen-Yi Lee
電子研究所
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Article
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引文 斯高帕斯（Scopus）
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Keyphrases
Processing Element
100%
Efficient Power
100%
Power Analysis
100%
Dual-field
100%
Cryptographic Processor
100%
Elliptic Curve Cryptography
100%
Dual Processing
100%
Scalar multiplication
40%
Power Analysis Attack
40%
Computational Complexity
20%
Wireless Channel
20%
90-nm CMOS Technology
20%
Hardware Efficiency
20%
Portable Applications
20%
Local Memory
20%
Processing Techniques
20%
Data Bandwidth
20%
Hardware Architecture
20%
Dedicated Hardware
20%
Private Key
20%
Synchronization Scheme
20%
High Demand
20%
Right versus Left
20%
GF-2
20%
Secure Information Exchange
20%
Processing Element Design
20%
Memory Synchronization
20%
Memory Hierarchy
20%
Side Channel Information Leakage
20%
Crypto
20%
Computer Science
Processing Element
100%
Power Analysis
100%
Elliptic Curve
100%
Scalar Multiplication
40%
Side Channel Attack
40%
Computational Complexity
20%
Wireless Channel
20%
Portable Application
20%
Hardware Architecture
20%
Dedicated Hardware
20%
side-channel
20%
Information Leakage
20%
Memory Hierarchy
20%
Computer Hardware
20%