摘要
A novel square-type layout style is proposed to efficiently implement CMOS output buffer with larger W/L ratio into a smaller silicon layout area than that of conventional finger-type layout style. Using this proposed layout style, the driving capability of CMOS output buffer in low-voltage submicron CMOS IC's can be effectively improved without increasing more layout area.
原文 | English |
---|---|
頁面 | 193-195 |
頁數 | 3 |
DOIs | |
出版狀態 | Published - 1995 |
事件 | Proceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology - Beijing, China 持續時間: 24 10月 1995 → 28 10月 1995 |
Conference
Conference | Proceedings of the 1995 4th International Conference on Solid-State and Integrated Circuit Technology |
---|---|
城市 | Beijing, China |
期間 | 24/10/95 → 28/10/95 |