Efficient Erase Operation by GIDL Current for 3D Structure FeFETs with Gate Stack Engineering and Compact Long-Term Retention Model

Fei Mo, Jiawen Xiang, Xiaoran Mei, Yoshiki Sawabe, Takuya Saraya, Toshiro Hiramoto, Chun Jung Su, Vita Pi Ho Hu, Masaharu Kobayashi*

*此作品的通信作者

研究成果: Article同行評審

1 引文 斯高帕斯(Scopus)

摘要

We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO2 field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL) current in erase operation of FeFETs with a floating body. We also introduced a novel gate stack process for low voltage operation by inserting a Ti layer in the metal gate. The Ti layer insertion can suppress the growth of an interfacial layer (IL) by controlling oxygen intrusion into the IL during the rapid thermal anneal (RTA) process. We demonstrated an efficient erase operation at shorter and lower pulse voltage with GIDL current in the overlap structure than in the underlap structure. A compact FeFET retention model is developed based on the surface-potential based FET model, the nucleation-limited-switching (NLS) model, and the retention model of ferroelectric (FE) capacitor. Faster degradation of the program state observed in the experiment can be explained by electron detrapping according to the modeling and simulation.

原文English
頁(從 - 到)115-122
頁數8
期刊IEEE Journal of the Electron Devices Society
10
DOIs
出版狀態Published - 2022

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