TY - JOUR
T1 - Efficient design for one dimensional discrete cosine transform using parallel adders
AU - Guo, Jiun-In
PY - 2000
Y1 - 2000
N2 - This paper proposes an efficient parallel adder based design for 1-D any-length discrete Cosine transform (DCT). Using the similar idea to the Chirp-Z transform, we develop an algorithm formulating the 1-D any-length DCT as cyclic convolutions. The proposed design using this algorithm not only owns higher flexibility in the transform length, but also possesses low hardware cost by using the parallel adder implementation. Considering an example using 16-bits coefficients, the proposed design can save much gate area as compared with other designs in the longer transform length applications.
AB - This paper proposes an efficient parallel adder based design for 1-D any-length discrete Cosine transform (DCT). Using the similar idea to the Chirp-Z transform, we develop an algorithm formulating the 1-D any-length DCT as cyclic convolutions. The proposed design using this algorithm not only owns higher flexibility in the transform length, but also possesses low hardware cost by using the parallel adder implementation. Considering an example using 16-bits coefficients, the proposed design can save much gate area as compared with other designs in the longer transform length applications.
UR - http://www.scopus.com/inward/record.url?scp=0033699025&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2000.857604
DO - 10.1109/ISCAS.2000.857604
M3 - Conference article
AN - SCOPUS:0033699025
SN - 0271-4310
VL - 5
SP - V-725-V-728
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
T2 - Proceedings of the IEEE 2000 International Symposium on Circuits and Systems
Y2 - 28 May 2000 through 31 May 2000
ER -