Efficient bit-parallel subcircuit extraction using CUDA

Che Lun Hung, Chun Yuan Lin*, Chia Shin Ou, Yuan Hong Tseng, Po Yen Hung, Ship Peng Li, Chun Ting Fu

*此作品的通信作者

研究成果: Article同行評審

2 引文 斯高帕斯(Scopus)

摘要

Wafer processing technology has been improving rapidly. Moore's law has been exceeded as the number of transistors in a dense integrated circuit, now increases threefold or more, approximately every year. The integrated circuit has gone from very large scale to giga large scale. The extraction of subcircuits has therefore become computation-intensive. In this paper, we propose an efficient bit-parallel subcircuit extraction algorithm using graphic processing units. We conducted experimental trials and demonstrated that the proposed algorithm can achieve high throughput, suggesting practical applications in the extraction of subcircuits.

原文English
頁(從 - 到)4326-4338
頁數13
期刊Concurrency Computation Practice and Experience
28
發行號16
DOIs
出版狀態Published - 1 11月 2016

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