Effects of spacer and single-charge trap on voltage transfer characteristics of gate-all-around silicon nanowire CMOS devices and circuits

Sekhar Reddy Kola, Yiming Li*, Narasimhulu Thoti

*此作品的通信作者

研究成果: Conference contribution › 同行評審

18 引文 斯高帕斯（Scopus）

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Keyphrases

Material Science

Engineering