Effective sleep transistor sizing algorithm for leakage power reduction

Power gating is one of the most effective methods for reducing leakage power. In this paper, an innovative and effective two-stage sleep transistor sizing algorithm for the distributed sleep transistor network (DSTN) structure is developed. To save execution time in stage one, a model order reduction based solver is extended and employed to evaluate the performance of DSTN, and sleep transistors are sized to obtain a suitable initial solution for stage two. In stage two, to make sure that the designed DSTN meets the required design constraints, the model order reduction based solver is replaced by an exact modified nodal analysis based solver. The criterion for choosing sleep transistors to be sized is decided by the maximum instantaneous source-drain voltage drop violation of each sleep transistor. The sizing amount of each picked sleep transistor is determined by the integral sensitivity of a performance metric of DSTN which simultaneously takes account of the temporal and spatial effects. The experimental results demonstrate that the proposed two-stage sleep transistor sizing algorithm outperforms the state-of-the-art method, the fine-grained sleep transistor sizing algorithm.