Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs with MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs

Shen Yang Lee, Han Wei Chen, Chiuan Huei Shen, Po Yi Kuo, Chun Chih Chung, Yu En Huang, Hsin Yu Chen, Tien Sheng Chao*

*此作品的通信作者

研究成果: Article同行評審

12 引文 斯高帕斯(Scopus)

摘要

In this article, we successfully fabricated nanowire (NW) negative capacitance (NC)-related ferroelectric FETs (FE-FETs) with two structures: trigate (TG) and gate-all-around (GAA). Planar capacitors with a metal-FE-metal (MFM) structure were investigated first. Post-metal annealing (PMA) at 700 °C resulted in the best ferroelectricity. This condition was considerably different from that of directly stacking onto NWs because of the difference in size and curvature between planar and TG or GAA structures. Because of the addition of an underlying ZrO2 seed layer, Hf1-x ZrxO2 in the gate-stack has been crystallized before the PMA process. In addition, two different gate-stack configurations, MFM-insulator-semiconductor (MFMIS) and metal-FE-insulator-semiconductor (MFIS), were investigated for the GAA structure. We determined that MFMIS displayed considerably more favorable subthreshold behavior and ON-state current compared with MFIS. NC-related phenomena, such as negative drain-induced barrier lowering and negative differential resistance, were observed.

原文English
文章編號8951114
頁(從 - 到)711-716
頁數6
期刊IEEE Transactions on Electron Devices
67
發行號2
DOIs
出版狀態Published - 2月 2020

指紋

深入研究「Effect of Seed Layer on Gate-All-Around Poly-Si Nanowire Negative-Capacitance FETs with MFMIS and MFIS Structures: Planar Capacitors to 3-D FETs」主題。共同形成了獨特的指紋。

引用此