Early load: Hiding load latency in deep pipeline processor

Shun Chieh Chang*, Walter Yuan Hwa Li, Yuan Jung Kuo, Chung-Ping Chung

*此作品的通信作者

研究成果: Conference contribution同行評審

4 引文 斯高帕斯(Scopus)

摘要

Load instructions usually have long execution latency in a deep processor pipeline, and have significant impact on overall performance. Therefore, how to hide the load latency becomes a serious problem in processor design. The latency of memory load can be separated into two parts: cache-miss latency and load-to-use latency. Previous work which tried to hide the load latency in a deep processor pipeline has some limitations. In this paper, we propose a hardware-based method, called early load, to hide the load-to-use latency with little hardware overhead. Early load scheme allows load instructions to load data from the cache system before it enters the execution stage. In the meantime, a detection method makes sure the correctness of the early operation before the load instruction enters the execution stage. Our experimental results showed that our approach can achieve 11.64% performance improvement in Dhrystone benchmark and 4.97% in average for MiBench benchmark suite.

原文English
主出版物標題13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008
DOIs
出版狀態Published - 2008
事件13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008 - Hsinchu, Taiwan
持續時間: 4 8月 20086 8月 2008

出版系列

名字13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008

Conference

Conference13th IEEE Asia-Pacific Computer Systems Architecture Conference, ACSAC 2008
國家/地區Taiwan
城市Hsinchu
期間4/08/086/08/08

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