An efficient early-late gate scheme for Bluetooth packet receiving had been proposed. It eliminates the use of Analogto-Digital Converter (ADC) and expends only hundred gate counts to implement the timing recovery. Simulation with complete Bluetooth V1.0 baseband and radio specifications had been established to confirm the timing recovery algorithm. Field programmable gate arrays (FPGA) emulation and ASIC implementation had all been completed for performance analysis.
|出版狀態||Published - 18 4月 2001|
|事件||2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings - Hsinchu, Taiwan|
持續時間: 18 4月 2001 → 20 4月 2001
|Conference||2001 International Symposium on VLSI Technology, Systems, and Applications, Proceedings|
|期間||18/04/01 → 20/04/01|